The present invention relates generally to a memory and, more specifically, to a method and apparatus for dynamically hiding a defect in a memory. The invented method and apparatus is particularly useful and suitable for a chip with an embedded memory.
Memory defects can result in malfunction of a system utilizing the defective memory and cause an abrupt shutdown without warning in advance, which not only takes the user considerable time, but also may cause unrecoverable loss. Unfortunately, there is a inevitably certain percentage of memory with memory defects. Usually a test is performed immediately after the manufacture of the chip, so that defective memory can be found and disposed of. However, disposing of defective memory leads to economic loss, and it is especially regrettable to discard a chip because of minor defects. The capacity of memory is increasing and the process technology is advancing continuously. For a chip with minor defects in memory to be usable instead of having to be discarded, a redundancy scheme is proposed to replace or repair the defective memory. Typically a redundancy scheme includes four procedures, i.e., testing, analyzing, repairing and retesting. A series of test signal patterns are applied to the memory to detect the position of a memory failure during the first procedure, and an analysis procedure follows to decide the optimum usage of the redundant memory. Then fuses are blown to define the connections and disconnections of the circuit in the repair procedure, and finally the repaired chip is retested to confirm that it functions correctly.
Even though repairing memory by using a redundancy scheme can reduce memory waste, the additional circuitry and fuses consume considerable chip area and complicate the circuit as well as the process. This not only increases the cost but also enlarges the chip. Furthermore, such repairing requires a lot of time on testing and analyzing, which further increases the time and cost. The problem due to memory defects is more severe for a chip with embedded memory because its circuitry is much more complicated than that of a stand-alone memory chip. A chip with embedded memory has a lot of circuitry around the memory, and it is thus more difficult to test the memory, and the tester is also more expensive and the test procedure is longer. Some schemes have been proposed to improve the situation. For example, U.S. Pat. No. 5,841,784 to Chan et al. discloses a method and circuit employing a switching circuit to temporarily couple an embedded memory in an integrated circuit to an interconnect pad during a memory test mode period to reduce test time and cost. U.S. Pat. No. 6,067,262 to Irrinki et al. provides a redundancy analysis methodology with built-in-self-test and built-in-self-repair so that an embedded memory can be tested on a standard logic tester and a detected field error can be related to its operation conditions. U.S. Pat. No. 6,073,258 to Wheater teaches a method and apparatus for executing two-dimensional redundancy computation to avoid collecting failure data during a test and repair procedure.
As the demand for larger embedded memory grows, the yield limitation imposed by the manufacturing process is also enlarged. Although a redundancy test is typically used as a functional test, this method often proves itself not enough or not applicable for larger embedded memory. Since it is more difficult to design and manufacture embedded memory, the loss caused by disposing of the chip due to memory defects therewith is larger, and it is thus desirable to decrease the number of chips with embedded memory that need to be discarded. U.S. Pat. No. 5,471,431 to McClure proposes a method and structure to define a functional part from an embedded memory by blowing fuses, which minimizes chip disposal though a smaller functional memory is obtained.
However, the above-mentioned prior art schemes can only filter out the defects found upon testing and fixed by repair, and any defects discovered or developed thereafter cannot be remedied and eventually the chip with memory defects in such manner must still be discarded. More seriously is that defects occurring in a memory after the test procedure will cause the chip to malfunction or a system to crash, thereby resulting in even larger loss. U.S. Pat. No. 5,764,878 to Kablanian suggests a built-in-self-repair system on a chip with embedded memory, which automatically executes the procedures of testing, repairing and retesting each time the computer system is powered up, and this method can therefore dynamically repair memory defects even it introduces large and complex circuitry into the chip and each power up of the computer system must go through those complicated and lengthy procedures. Moreover, the address table of the memory must be configured each time for the Kablanian scheme. These inconveniences render this technique impractical and the system will crash once there are too many defects, exceeding what the redundant circuit can repair. U.S. Pat. No. 6,192,486 issued to Correale, Jr. et al. provides a memory defect steering circuit that does not carry out fuse-blowing repair, but detects and bypasses a defective memory each time the computer system boots up, and then recalculates the size of the functional memory, and modifies the memory addresses. While this method decreases the memory size, it can dynamically exclude memory defects. However, it is inconvenient to recalculate the effective memory size and modify the memory addresses, and the extra circuitry to modify the memory address occupies considerable chip area. Furthermore, due to the fact that its memory address space is continuous, remapping the memory address cannot exclude a single memory defect, but instead starts from the next available entry following the defective entry, and thus the entries before the defective memory are wasted.
The present invention is proposed to overcome the above-mentioned problems by masking memory defects, instead of repairing the defective memory by blowing fuses, and thus to avoid the lengthy procedures of testing, repairing and retesting. The invented scheme may also result in a reduction of memory volume, and makes it possible to use defective chips and not to dispose of them.
One feature of the present invention is to employ a simple and straightforward method and apparatus to exclude memory defects.
One feature of the present invention is to reduce the need for chip disposing due to memory defects therewith.
One feature of the present invention is to dynamically exclude memory defects by discovering and hiding the memory defects each time the chip with the memory defects is powered up.
One feature of the present invention is to avoid large and redundant circuitry introduced into the memory chip for excluding memory defects therewith.
One feature of the present invention is to avoid recalculating memory size and addresses resulting from the memory defects.
One feature of the present invention is to preserve the functional circuit on a chip with embedded memory.
One feature of the present invention is to avoid the necessity to repair memory.
In one embodiment of the present invention, an initial test is conducted on a memory to discover defective entries, an entry occupied mapping is prepared that contains a plurality of fields where each filed corresponds to an entry of the memory, and an initialization control apparatus is used to mark the fields corresponding to defective entries to make them be perceived as occupied so that the defective entries will not be accessed until the system is shut down.
In another embodiment of the present invention, a backup memory or backup register pool is provided and an error entry recorder/controller is used to record error entries and pick up a pseudo entry from the backup memory or backup register pool for corresponding to each respective error entry after the memory goes through an initial test. A subsequent access to an error entry results in a redirect to the corresponding pseudo entry.